Since a 4- stage shift register is shown above, four clock pulses are required to shift out all of the data. The data is then shifted out via “data out” by clock pulses. The “first in” data is “first out” as it is shifted from “data in” to “data out”.ĭata is loaded into all stages at once of a parallel-in/serial-out shift register. After the third clock, stage C is replaced by stage B stage B is replaced by stage A and stage A is replaced by “data in”.Īfter the fourth clock, the data originally present at “data in” is at stage D, “output”. After the second pulse stage A data is transfered to stage B output, and “data in” is transfered to stage A output. Longer shift registers, with the help of feedback generate patterns so long that they look like random noise, pseudo-noise.īasic shift registers are classified by structure according to the following types:Ībove we show a block diagram of a serial-in/serial-out shift register, which is 4-stages long.ĭata at the input will be delayed by four clock periods from the input to the output of the shift register.ĭata at “data in”, above, will be present at the Stage A output after the first clock pulse. Some specialized counter circuits actually use shift registers to generate repeating waveforms. Numerous peripherals, including analog to digital converters, digital to analog converters, display drivers, and memory, use shift registers to reduce the amount of wiring in circuit boards. Serial data over shorter distances of tens of centimeters, uses shift registers to get data into and out of microprocessors. Serial data communications replaces many slow parallel data wires with a single serial high speed circuit. Serial data transmission, over a distance of meters to kilometers, uses shift registers to convert parallel data to serial form. This obsolete application is reminiscent of the acoustic mercury delay lines used as early computer memory. The stages in a shift register are delay stages, typically type “D” Flip-Flops or type “JK” Flip-flops.įormerly, very long (several hundred stages) shift registers served as digital memory.

Thus, a four stage shift register delays “data in” by four clocks to “data out”.

Shift registers produce a discrete delay of a digital signal or waveform.Ī waveform synchronized to a clock, a repeating square wave, is delayed by “n” discrete clock times, where “n” is the number of shift register stages. In other words, sequential logic remembers past events. Sequential logic, unlike combinational logic is not only affected by the present inputs, but also, by the prior history. Shift registers, like counters, are a form of sequential logic.

Labview shift registers